JSSC 2012第11期Data Converters65nmSAR ADCDAC

A 50-fJ 10-b 160-MSs Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embed

一种采用时间交织流水线-SAR ADC和片上偏移消除技术的低功耗设计。

65nm CMOS, 1.1V, 160MS/s, 55.4dB SNDR, 2.72mW

流水线-SAR ADC时间交织偏移消除电容DAC低功耗

▸SAR ADC重复用于偏移消除以节省校准成本

▸采用翻转操作的6位电容DAC实现8倍级间增益

▸电容衰减技术显著降低功耗并优化转换速度

Abstract

This paper presents a time-interleaved pipelined-SAR ADC with on-chip offset cancellation technique. The design reuses the SAR ADC to perform offset cancellation, thus saving calibra- tion costs. The inter-stage gain of 8 is implemented in a 6-bit ca- pacitive DAC with a ﬂip-around operation. A capacitive attenua- tion used in both the ﬁrst and second DACs signi ﬁcantly reduces the power dissipation and optimizes conversion speed. The detailed circuit implementation of the subthreshold op-amp is