A Near-Optimum Dynamic V oltage Scaling (DVS) in 65-nm Energy-Ef ficient Power Management With Frequency-Based Control (FBC) for SoC System Yu - H u e i L e e,S t u d e n tM e m b e r ,I E E E, Chao-Chang Chiu , Student Member , IEEE, Shen-Y u Peng

Abstract

A 65-nm energy-ef ficient power management with frequency-based control (FBC) is p roposed to achieve the near-op- timum dynamic voltage scaling (DV S) in a system-on-chip system. Since DVS and dynamic frequenc y scaling (DFS) operations are demanded for system processor, control loop of the proposed single-inductor dual-output (SIDO) power module is merged with the frequency-controlled phase-locked loop (PLL) to constitute the operation of hybrid control loop. This means that both DVS and DFS operations can be guaranteed and are not affected by process, supply voltage, and temperature variations. The proposed power management can receive the demand of system processor by hybrid control loop and can help realize the supply voltage with different operation tasks for near-optimum DVS operation. The fabricated chip occupies a 1.12-mm silicon area. Experi- mental results show that the SIDO power module achieves a peak efficiency of 90% and the highest power reduction of 33% with the proposed near-optimum DVS operation.