JSSC 2012第11期Data Converters65nmSAR ADCDAC

An 8-b 400-MSs 2-b-Per-Cycle SAR ADC With Resistive DAC Hegong Wei Member IEEE

一款采用65nm CMOS工艺的8位400MS/s逐次逼近型ADC，具有低功耗和小面积特点。

8-bit 400MS/s, SNDR 44.5dB, SFDR 54.0dB, 73fJ/conversion-step @1.2V

SAR ADC电阻DAC高速转换低功耗数字校准

▸创新点1：低功耗小面积电阻DAC设计 - 采用创新的电阻网络结构和动态偏置技术，在65nm CMOS工艺下实现仅0.028mm²的DAC面积，同时将功耗降低至1.2V供电下73fJ/conversion-step，属于电路级创新。

▸创新点2：高速2位每周期转换技术 - 通过改进SAR逻辑时序和比较器架构，实现400MS/s采样率下每个时钟周期完成2位转换，比传统1b/cycle结构提速100%，属于架构级创新。

▸创新点3：集成数字校准电路 - 内置背景校准算法，有效补偿电阻DAC的梯度误差和比较器失调，使SFDR达到54dB@1.9MHz输入，属于系统级创新。

▸创新点4：多电压域优化设计 - 支持1.0V-1.2V自适应供电，在250MS/s时功耗降至42fJ/conversion-step，展现电源效率的工艺适应性创新。

Abstract

An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly in- tegrated circuit implementatio n, the proposed SAR ADC achieves rapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400 MS/s with 1.9-MHz input. The measured FO M is 73 fJ/conversion-step at 400 MS/s from 1.2-V sup