An 80-Gbs HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors

Abstract

We present an 8.0-Gb/s HyperTransport source-syn- chronous I/O integrated in a 32-nm SOI-CMOS processor for high-performance servers. Ba sed on a 45-nm design capping at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels by inc orporating several jitter- and power-reduction enhancements. First, a high-bandwidth digital clean-up PLL is introduced to attenuate high-frequency jitter in the received forwarded clock before the data is sampled. This PLL achieves a h