An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors Alvin L. S. Loke , Senior Member , IEEE , Bruce A. Doyle , Senior Member , IEEE , Sanjeev K. Maheshwari , Member , IEEE, Dennis M. Fischette , Senior Member , IEEE, Charles L. Wang, Tin

Abstract

We present an 8.0-Gb/s HyperTransport source-syn- chronous I/O integrated in a 32-nm SOI-CMOS processor for high-performance servers. Ba sed on a 45-nm design capping at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels by inc orporating several jitter- and power-reduction enhancements. First, a high-bandwidth digital clean-up PLL is introduced to attenuate high-frequency jitter in the received forwarded clock before the data is sampled. This PLL achieves a highly programmable jitter bandwidth of 20–296 MHz ( m e a s u r e dw i t h0 . 2 input jitter) and 0.90–1.50 ps output rms jitter by implementing an ext ended bang-bang phase detector for additional phase-error magnitude information and flexible bang–bang control of a current-s tarved ring-based oscillator. Second, several power-hungry circuits, namely the transmitter input FIFO and output driver as we ll as the receiver deserializer, are redesigned for 8.0-Gb/s operation to maintain thermal com- patibility with the existing 45-nm socket package. The fabricated 20-lane I/O consumes 1.70 W at 8.0 Gb/s with an energy ef ficiency of 11.8 pJ/bit. This re flects a 4.9% increase i n HyperTransport power consumption and only 0.3 % increase in total processor target power relative to 45-nm operation at 6.4 Gb/s.