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CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation
提出一种无需参考时钟的高时间分辨率片上时序抖动测量电路，采用自参考时钟和级联时间差放大器。
时间分辨率31fs（带TDA）/2.8ps（不带TDA）
时序抖动测量自参考时钟时间差放大器CMOS电路占空比补偿
▸创新点1：自参考时钟消除外部参考时钟需求（系统创新）。通过生成时钟周期的倍数作为自参考时钟，完全消除了对外部高精度参考时钟的依赖，实现了全集成化测量系统，在65nm和40nm工艺下分别实现1350μm²和470μm²的紧凑面积。
▸创新点2：级联时间差放大器提高时间分辨率（电路创新）。采用多级TDA级联结构显著提升时间测量分辨率，配合65nm工艺实现31fs的超高分辨率，相比传统结构(2.8ps)提升两个数量级，同时保持GHz级操作速度。
▸创新点3：占空比补偿技术保持操作速度（方法创新）。在级联TDA中创新性地引入动态占空比补偿机制，有效解决了时间放大过程中的信号畸变问题，使系统在31fs分辨率下仍能维持稳定工作。
▸创新点4：全数字化架构实现工艺可移植性（系统创新）。提出的纯数字电路架构在65nm和40nm工艺节点均成功验证，40nm工艺下面积缩减至112μm²(TDA关闭时)，展现优异的工艺适应性。
Abstract
This paper describes a reference-clock-free, high- time-resolution on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference ampli fier (TDA) with duty-cycle compensation. A self-referenced clock with multiples of the clock period r emoves the necessity for a reference clock. In addition, a cascaded TD A with duty-cycle compensation improves the time resolution while maintaining the operational speed. Test chips were desig ned and fabricated using 65 nm and 40 nm CMOS technologies. The areas occupied by the circuits are 1350 m (with TDA, 65 nm), 490 m (without TDA, 65 nm), 470 m (with TDA, 40 nm), and 112 m (without TDA, 40 nm). Time resolutions of 31 fs (with TDA) and 2.8 ps (without TDA) were achieved. The proposed new architecture provides all-digital timing jitter measu rement with fine-time-resolution measurement capability, without requiring a reference clock.