A 16-mW 78-dB SNDR 10-MHz BW CT ADC Using Residue-Cancelling VCO-Based Quantizer Karthikeyan Reddy, Student Member , IEEE ,S a c h i n R a o, Student Member , IEEE , Rajesh Inti, Student Member , IEEE, Brian Y oung, Student Member , IEEE,A m r E l s h a z l y, Student Member , IEEE, Mrunmay Talegaonkar, Student Member , IEEE, and Pavan

Abstract

This paper presents a continuous-time (CT) modulator using a VCO-based inte rnal quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue canceling quantizer (RCQ) and mitigates the impact of its non- linearity by spanning only a small region of the VCO’s V-to-F nonlinear tuning curve. The order of noise shaping is increased by placing the RCQ in a continuous-time loop. Using only a first order loop filter, the proposed modulator achieves second order noise shaping. Fabricat ed in a 90-nm CMOS process, the prototype modulator occupies an active area of 0.36 mm and consumes 16 mW power. It achieves a peak SNDR of 78.3 dB in 10-MHz bandwidth and an SFDR of better than 85 dB when clocked at 600 MHz. The figure of merit of the modulator is 120 fJ/conv-step.