← 返回 JSSC 论文列表JSSC 2012第12期Data Converters40nmSAR ADC
A 17 mW 11b 250 MSs 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm
40纳米工艺下17mW功耗、11位精度、250MS/s采样率的2倍交织全动态流水线SAR ADC
62dB SNDR@10MS/s, 56dB SNDR@250MS/s, 7-10fJ/转换步
SAR ADC交织采样动态残差放大冗余校准低功耗
▸创新点1：采用2倍交织结构（2x interleaved）实现250 MS/s的高采样率，通过时间交替采样技术有效提升系统吞吐量，属于系统级创新。该设计在40 nm工艺下实现了17 mW的低功耗表现，同时保持11位精度。
▸创新点2：动态残差放大器（dynamic residue amplifier）的创新设计优化了转换精度，结合校准技术补偿增益不确定性，使ADC在250 MS/s Nyquist输入下仍保持56 dB SNDR，属于电路级创新。
▸创新点3：冗余位设计（2 bits redundancy）增强了系统鲁棒性，通过6位粗SAR与7位细SAR的级联结构实现11位分辨率，并利用冗余位容错机制降低比较器噪声影响，属于方法创新。
▸创新点4：能效优化方面，通过动态流水线架构实现7 fJ/conversion-step@10MS/s至10 fJ/conversion-step@250MS/s的超低能耗，属于电路-系统协同创新。
Abstract
A 250 MS/s 2x interleaved 11 bit pipelined SAR ADC
in 40 nm digital CMOS is presented. Each ADC channel consists
of a 6b coarse SAR, a dynamic residue ampli fier and a 7b fine SAR
with a total of two bits of redundancy. Calibration is leveraged to
adjust the uncertain gain of the chosen residue ampli fier and var-
ious other non-idealities. The ADC achieves a peak SNDR of 62 dB
at 10 MS/s, and 56 dB for a Nyquist input at 250 MS/s. The low
frequency energy per conversion step ranges from 7 fJ at 10