A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

Abstract

This paper presents the design of a 19-Gb/s serial l i n kr e c e i v e rw i t hb o t h4 - t a pf e e d - f o r w a r de q u a l i z e r( F F E )a n d 5-tap decision-feedback equalizer (DFE), thereby m aking the equalization system self-contained in the receiver. This design extends existing power-ef ficient DFEs based on current-inte- grating summers and add s FFE functionality t ot h eD F Ec i r c u i t infrastructure for an ef ficient implementation. Key techniques for implementing receive-side FFE are: the use of multiphase quarter-rate sample-and-hold circuits f or generating multiple time-shifted input data signals, ti me-based analog multiplication for FFE coef ficient weighting, and a merged FFE/DFE summer. The receiver test chip, implemente d in a 45-nm silicon-on-insu- lator (SOI) CMOS technology, occupies 0.07 mm and has a power efficiency of 6.2 mW/Gb/s at 19 Gb/s. Step-reponse characteriza- tion of the receiver demonstrate s accurate FFE computation. The receiver equalizes a 35-in PCB trace at 17 Gb/s with a channel loss of 30 dB at 8.5 GHz and a 20-in PCB trace at 19 Gb/s with a channel loss of 25 dB at 9.5 GHz.