A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology John F. Bulzacchelli, Member , IEEE,C h r i s t i a n M e n o lfi, Member , IEEE, Troy J. Beukema , Member , IEEE, Daniel W. Storaska , Member , IEEE, Jürgen Hertle , Member , IEEE, David R. Hanson

Abstract

This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forward equalizer (FFE) in t he transmitter and a two-stage peaking ampli fier and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series termi- nated (SST) driver topology which doubles the speed of existing half-rate designs. The high-frequency boost provided by the peaking ampli fier is enhanced by adopting a structure with ca- pacitively coupled parallel input stages and active feedback. A capacitive level-shifting technique is introduced in the half-rate DFE which allows a single current-integrating summer to drive the four parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated with the trans- ceiver over a channel with 35 dB los s at half-baud frequency. In a four-port core con figuration, the power consumption at 28 Gb/s is 693 mW/lane.