JSSC 2012第12期RF & Wireless0.13μm CMOS

A 28.3 mW PA-Closed Loop for Linearity and Efﬁciency Improvement Integrated in a 27.1 dBm WCDMA CMOS Power Ampli ﬁer Shouhei Kousai, Kohei Onizuka, Takashi Y amag uchi, Y asuhiko Kuriyama, and

提出一种宽带反馈线性化技术（PA-closed loop），用于提高功率放大器（PA）的线性度和效率。

WCDMA输出功率27.1 dBm，功率附加效率（PAE）28%，ACLR 40 dBc

功率放大器反馈线性化宽带WCDMACMOS

▸创新点1：两路径反馈方案（方法创新）。通过同时检测输入和输出的相位与振幅，直接在射频（RF）进行对比控制，实现PA的线性化。这种方案不仅简化了传统反馈结构的复杂度，还显著提升了宽带操作的稳定性，适用于高频应用场景。

▸创新点2：宽带特性抑制相邻信道泄漏比（ACLR）（性能创新）。通过宽带反馈环路的设计，将WCDMA标准的ACLR降低了6 dB，显著提升了信号纯净度，适用于高要求的通信标准。

▸创新点3：降低静态功耗（电路创新）。该闭环设计仅消耗28.3 mW的功耗，同时将PA的静态功耗降低了78 mW，显著提升了整体能效，适合移动设备等低功耗应用。

▸创新点4：负载变化下的性能稳定性（系统创新）。在电压驻波比（VSWR）为1.5时，所需回退仅降低1 dB，而无环路时为3 dB，展现了系统在复杂负载条件下的鲁棒性。

Abstract

Aw i d e b a n df e e dback linearization technique for a power ampli ﬁer (PA), PA-closed loop , is presented. In order to achieve wideband operation, i t employs a two-path feedback scheme where the inp ut and output phases and amplitudes are de- tected at RF and compared to directly control and linearize the PA. The wideband characteristic of the loop suppressed the adjacent channel leakage r atio (ACLR) for WCDMA standard by 6 dB. The advantage of the feedback is d emonstrated by measuring the performance against t he load variation. The required back-off is degraded by only 1 dB with a voltage standing wave ratio (VSWR) of 1.5, whereas it is 3 dB without the loop. The loop consumes 28.3 mW and it reduces the quiescent power consumption of the PA by 78 mW. The ch ip, which integrates the loop and PA, is fabricated in a 0.13 m CMOS technology and the loop occupies 0.3 mm by 0.7 mm. The PA delivers WCDMA output power of 27.1 dBm with a power added efﬁciency (PAE) of 28% and ACLR of 40 dBc. This topology makes possible the wide band feedback linearization of a watt-level PA.