A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel

Abstract

This paper introduces a novel signaling sch eme for parallel high-speed interfaces. The new signaling, called coded dif- ferential (CD), maps two bits of information to four wires and, therefore, has the same pin-ef ficiency as differential signaling. The coding scheme is designed in such a way that the parallel inter- face preserves many of the attracti ve properties of a differential link such as low supply noise generation and immunity to common- mode noise. The CD receiver also incorporates differential detec- tion with no need for a dc reference. In addition, the coding com- pletely eliminates the first post-cursor intersymbol interference of the channel over the entire unit-interval at no loss in throughput. As a result, CD leads to substantial increase in timing margin com- pared with a differential link wit h1 - t a pd e c i s i o nf e e d b a c ke q u a l - izer (DFE). Unlike DFE, CD does not require channel tap estima- tion. The theory of CD signaling, the optimization of the encoder and the decoder, and the impleme ntation details of a prototype system developed based on this scheme for graphics memory in- terfaces are described. The full-featured interface, implemented in a 40-nm CMOS process, trans fers 8 16 Gb/s data over 16 wires and achieves an energy ef ficiency of 4.1 pJ/b. Eye diagram mea- surements on a scope indicate 30% improvement in timing margin compared with a 1-tap pre dictive DFE system.