A Dual-Channel 23-Gbps CMOS Transmitter/ Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission Delong Cui, Bharath Raghavan, Ullas Singh, Anand V asani, Zhi Huang

Abstract

This paper describes a dual-channel 23 (20 to 27) Gbps chipset designed in a 40-nm CMOS process for 40 Gbps differential quadrature phase-shift keying (DQPSK) optical trans- mission. The transmitter has a 2-tap FIR filter and generates two channels of full-rate data. Data outputs exhibit 10 ps rise/fall times, 0.2 RJ, 0.8 DJ, and a 0.5 UI skew adjust- ment relative to the full-rate and half-rate clock outputs. The receiver has two 20–27-Gbps input channels, with each channel including a peaking filter, decision threshold adjustment, and 1-tap loop-unrolled DFE. It achieves a 7- input sensitivity and a 0.7- high-frequency jitter tol erance. The transmitter and receiver dissipate 0.63 and 1.2 W, respectively.