← 返回 JSSC 论文列表JSSC 2012第12期Data Converters90-nm
Design Techniques for Wideband Single-Bit Continuous-Time Modulators With FIR Fe
设计宽频带单比特连续时间调制器的FIR反馈技术
71-dB SNDR, 36-MHz带宽, 15 mW功耗, 1.2-V电源, 3.6 GS/s采样率
连续时间Delta-Sigma调制器FIR反馈DAC单比特量化器低抖动灵敏度高线性度
▸使用FIR反馈DAC的单比特调制器设计
▸结合单比特和多比特调制器的优势
▸补偿FIR-DAC引入的延迟的环路方法
Abstract
We give design considerations for single-bi tc o n t i n -
uous-time Delta–Sigma modulators (CTDSMs) with FIR feedback
DACs. These modulators have the low jitter sensitivity and high
linearity properties characteristic of a mult ibit modulator, while
using a simple one-bit quantizer, thereby combining the advan-
tages of single-bit and multibit operation. We propose a method
to compensate the loop for the delay introdu ced by the FIR-DAC.
The ef ficacy of our architectural and circuit techniques