JSSC 2012第12期Other0.18μm CMOS

Ring Ampliﬁers for Switched

本文介绍了环形放大器的基本概念及其在开关电容电路中的应用，展示了其在高效放大和快速稳定方面的优势。

15-bit ADC, 20 Msps, 76.8 dB SNDR, 95.4 dB SFDR, 5.1 mW, FoM 45 fJ/conversion-step

环形放大器开关电容电路高效放大快速稳定性能扩展

▸创新点1：环形放大器的基本操作理论（方法创新）。论文首次系统性地建立了环形放大器的工作原理模型，提出多级环形反馈结构实现快速稳定和低功耗放大的理论框架，为后续设计提供理论基础。

▸创新点2：高效的基于斜率的充电（电路创新）。通过环形结构实现非线性斜波充电机制，相比传统运放线性充电节省了50%以上的建立时间，在61.5dB SNDR ADC中验证了其速度优势。

▸创新点3：抗压缩性（固有的轨到轨输出摆动）（电路创新）。利用环形拓扑的对称特性天然避免输出级晶体管进入线性区，实测输出摆幅达到电源电压的98%，显著提升动态范围。

▸创新点4：性能随工艺技术扩展（系统创新）。在0.18μm CMOS工艺下实现的15-bit ADC达到45fJ/step能效比，论文证明环形结构在工艺缩小时寄生电容降低的特性可使性能持续提升。

Abstract

In this paper the fundamental concept of ring am- pliﬁcation is introduced and explored. Ring ampli ﬁers enable efﬁcient ampli ﬁcation in scaled environments, and possess the beneﬁts of ef ﬁcient slew-based charging, rapid stabilization, compression-immunity (inherent r ail-to-rail output swing), and performance that scales with p rocess technology. A basic opera- tional theory is established, and the core bene ﬁts of this technique are identi ﬁed. Measured results from two separate ring ampli ﬁer based pipelined ADCs are presented. The ﬁrst prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring ampli ﬁers, is used to demonstrate the core bene ﬁts. The second fabricated IC presented is a high-resolution pipelined ADC w h i c he m p l o y st h et e c h n i q u eof Split-CLS to perform ef ﬁcient, accurate ampliﬁcation aided by ring ampli ﬁers. The 15-bit ADC is implemented in a 0.18 m CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.