JSSC 2013第1期Memory30nmDRAM

A1 2V3 0n m3 2G b s p i n4G bD D R 4S D R A M With Dual-Error Detection and

1.2V 4Gb DDR4 SDRAM采用30nm CMOS工艺，通过双错误检测方案提升信号可靠性，实现3.3Gb/s高速操作。

30nm CMOS, 1.2V, 3.3Gb/s

DDR4 SDRAM双错误检测低功耗高速信号30nm CMOS

▸双错误检测方案（CRC和CA奇偶校验）

▸增益增强缓冲器和PVT容忍数据获取方案

▸根据数据速率选择延迟线类型以减少输出抖动

Abstract

A 1.2 V 4 Gb DDR4 SDRAM is presented in a 30 nm CMOS technology. DDR4 SDRAM is developed to raise memory bandwidth with lower power consumption compared with DDR3 SDRAM. Various functions and ci rcuit techniques are newly adopted to reduce power consumpt ion and secure stable transac- tion. First, dual error detection scheme is proposed to guarantee the reliability of signals. It is composed of cyclic redundancy check (CRC) for DQ channel and command-address (CA) parity for command and address c