A 2.05 GV ertices/s 151 mW Lighting Accelerator for 3D Graphics V ertex and Pixel Shading in 32 nm CMOS

Abstract

This paper describes a single-cycle throughput lighting accelerator fabricated in 1.05 V , 32 nm CMOS for on-die acceleration of 3D graphics vert ex and pixel shading in high-per- formance processors and mobile systems-on-chip. Log-domain parallel computation of ambient, diffuse, and specular lighting using high-accuracy 32b log and anti-log units that convert computation from floating-point (FP) to fixed-point domain, 32b sparse-tree fixed-point adders and a 32 32b signed fixed-point multiplier with truncated partial product reduction tree enable 2.05 GVertices/s throughput measured at 1.05 V , 25 Ci na na r e a of 0.064 while achieving: (i) 47% reduction in critical path logic stages compared to previously published work, (ii) 0.56% mean vertex lighting error com pared to single-precision FP computation, (iii) 354 W active leakage power measured at 1.05 V , 25 C, (iv) scalable performance up to 2.22 GHz, 232 mW measured at 1.2 V , (v) peak energy-ef ficiency of 56 GV ertices/s/W, measured at 560 mV , 25 C, and (vi) 119.6 dB PSNR for a 2 M pixel high-resolution 3D image.