Abstract
An ultra-low voltage recon figurable 4-way to 32-way SIMD vector permutation engine is fab r i c a t e di n2 2n mt r i - g a t e bulk CMOS, consisting of a 32-entry 256b 3-read/1-write ported register file with a 256b byte-wise any-to-any permute crossbar for 2-dimensional shuffle. The register file integrates a vertical shuf fle across multiple entries into read/ write operations, and includes clock-less static reads with shared P/N dual-ended transmission gate (DETG) writes, improving r egister file by 250 mV across PVT variations with a wide dynamic operating range of 280 mV-1.1 V. The permute crossbar implements an interleaved folded byte-wise multiplexer layout forming an any-to-any fully connected tree to perform a horizontal shuf fle with permute accu- mulate circuits, and includes vector flip-flops, stacked min-delay buffers, shared gates, and ul tra-low voltage split-output (ULVS) level shifters improving logic by 150 mV , while enabling peak energy ef ficiency of 585 GOPS/W measured at 260 mV , 50 C. The permutation engi ne achieves: (i) nominal register file performance of 1.8 GHz, 106 mW measured at 0.9 V , 50 C, (ii) robust register file functionality measured down to 280 mV with peak energy ef ficiency of 154 GOPS/W, (iii) scalable permute crossbar performance of 2.9 GHz, 69 mW measured at 1.1 V , 50 C with sub-threshold operation at 240 mV , 10 MHz consuming 19 W, and (iv) a 64b 4 4m atrix transpose algorithm and AoS to SoA conversion with 40%–53% energy savings and 25%–42%