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JSSC 2013第1期Clocking & PLLs22nm

A 280 mV-to-11 V 256b Recon figurable SIMD V ector Permutation Engine With 2-Dime

一款超低压可重构SIMD向量排列引擎，支持280mV至1.1V宽动态范围操作。
22nm CMOS, 280mV-1.1V, 2.9GHz@1.1V, 585GOPS/W@260mV
超低压SIMD可重构排列寄存器文件能量效率
▸集成垂直与水平排列的2D可重构排列引擎
▸采用共享P/N双端传输门写入的时钟无关静态读取寄存器文件
▸超低压分路输出电平转换器提升150mV逻辑性能
Abstract
An ultra-low voltage recon figurable 4-way to 32-way SIMD vector permutation engine is fab r i c a t e di n2 2n mt r i - g a t e bulk CMOS, consisting of a 32-entry 256b 3-read/1-write ported register file with a 256b byte-wise any-to-any permute crossbar for 2-dimensional shuffle. The register file integrates a vertical shuf fle across multiple entries into read/ write operations, and includes clock-less static reads with shared P/N dual-ended transmission gate (DETG) writes, improving r egister file