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A 46 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Re
22nm三栅极CMOS技术中的162Mb SRAM设计，支持电压缩放，优化低频低压性能
22nm CMOS, 1.0V/0.8V, 4.6GHz/3.4GHz, 6.7Mb/mm²
SRAM三栅极CMOS电压缩放bitcell设计低频优化
▸0.092μm高密度bitcell设计
▸0.108μm低压高性能bitcell设计
▸瞬态电压崩溃和字线欠驱动辅助电路
Abstract
A 162 Mb voltage-scalable SRAM array design in
22 nm CMOS tri-gate logic technol ogy is presented. The designs of
a 0.092 m bitcell for high density applications and a 0.108 m
bitcell for improved performance at low supply voltage are in-
troduced. Transient voltage collapse and wordline under-drive
peripheral assist circuits impr ove low-voltage operating margins
and address fin quantization. Co-optimization of tri-gate tran-
sistors and circuits allow up t o 70% improvement in frequency
at low