A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write

Abstract

A 162 Mb voltage-scalable SRAM array design in 22 nm CMOS tri-gate logic technol ogy is presented. The designs of a 0.092 m bitcell for high density applications and a 0.108 m bitcell for improved performance at low supply voltage are in- troduced. Transient voltage collapse and wordline under-drive peripheral assist circuits impr ove low-voltage operating margins and address fin quantization. Co-optimization of tri-gate tran- sistors and circuits allow up t o 70% improvement in frequency at low voltages and 85% improvement in density from a scaled 32 nm design. The low-voltage array design demonstrates 4.6 GHz operation at 1.0 V and 3.4 GHz operation at 0.8 V while achieving array densities up to 6.7 Mb/mm .