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JSSC 2013第1期Other0.18µm

An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput Akifumi Kawahara, Ryotaro Azuma, Y uuichirou Ike da, Ken Kawai, Y oshikazu Katoh, Y ukio Hayakawa, Kiyotaka Tsuji, Shinichi Y oneda, Atsushi Himeno, Kaz uhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, and

开发了8Mb多层交叉点ReRAM宏,写入吞吐量达443MB/s,采用TaOx ReRAM和新写入架构。
8Mb, 443MB/s写入吞吐量, 64-bit并行写入, 17.2ns周期
ReRAM多层交叉点TaOx写入吞吐量分层位线
双向二极管作为存储单元选择元件
PMOS和NMOS用于源极跟随器选择晶体管
分层位线结构和多比特写入架构
Abstract
An 8-Mb multi-layered cross-point resistive RAM (ReRAM) macro has been developed with 443 MB/s write throughput (64-bits parallel write per 17.2-ns cycle), which is al- most twice as fast as competing me thods. It uses th e fast switching performance of TaOx ReRAM and a new write architecture to reduce the sneak current in a cross-point cell array structure based on an 0.18-µm process. Fi rst, a bidirectional diode as a memory cell select element is developed to reduce the sneak current. Second, PMOS and NMOS are used select transistors in the source follower to realize stable switching for the selected cell in the multi-layered cross-point structure. Third, a hierarchical bitline (BL) structure is employed with a short bitline. Fourth, multi-bit write architecture is developed to realize fast write operation and to suppress the sneak current.