Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction Matthew Fojtik, David Fick, Y ejoong Kim, Na thaniel Pinckney, David Money Harris

Abstract

We propose Bubble Razor, an architecturally inde- pendent approach to timing error detection and correction that avoids hold-time issues and enables large timing speculation win- dows. A local stalling technique that can be automatically inserted into any design allows the system to scale to larger processors. We implemented Bubble Razor on an ARM Cortex-M3 micropro- cessor in 45 nm CMOS without detailed knowledge of its internal architecture to demonstrate the technique’s automated capability. The flip-flop based design was converted to two-phase latch timing using commercial retiming tools; Bubble Razor was then inserted using automatic scripts. This system marks the first published im- plementation of a Razor-style scheme on a complete, commercial processor. It provides an energy ef ficiency improvement of 60% or a throughput gain of up to 100% compared to operating with worst case timing margins.