CMOS Image Sensor With Per-Column ΣΔ ADC and Programmable

Abstract

A CMOS image sensor architecture with built-in single-shot compressed sensing is described. The image sensor employs a conventional 4-T pixel and per-column ΣΔ ADCs. The compressed sensing measurements are obtained via a column multiplexer that sequentially a pplies randomly selected pixel values to the input of each ΣΔ modulator. At the end of readout, each ADC outputs a quantized value of the average of the pixel values applied to its input. The image is recovered from the random linear measurements off-c hip using numerical optimiza- tion algorithms. To demonstrate t his architecture, a 256x256 pixel CMOS image sensor is fabricated in 0.15 µm CIS process. The sensor can operate in compressed sensing mode with compression ratio 1/4, 1/8, or 1/16 at 480, 960, or 1920 fps, respectively, or in normal capture mode with no compressed sensing at a maxi mum frame rate of 120 fps. Measuremen t results demonstrate capture in compressed sensing mode at rou ghly the same readout noise of 351 µV and power consumption of 96.2 mW of normal captu re at 120 fps. This performance is a chieved with only 1.8% die area overhead. Image reconstruction shows modest quality loss relative to normal capture and signi ficantly higher image qu ality than downsampling.