The Next Generation 64b SPARC Core in a T4 SoC Processor Jinuk Luke Shin, Robert Golla, Hongping Li, Sudesna Dash, Y oungmoon Choi, Al an Smith, Harikaran Sathianathan, Mayur Joshi, Heechoul Park , Mohamed Elgebaly, Sebastian Turullols, Song Kim, Robert Masleid, Georgios K. Konstadinidis, Mary Jo Doherty, Greg Grohoski , and Curtis McAllister

Abstract

The SPARC T4 processor introduces the next gen- eration multi-threaded 64b core to deliver up to 5x integer and 7x floating-point single-thread pe rformance improvement over its predecessor. The chip integrates eight cores, an 8-Bank 4 MB L3 Cache, a 768 GB/sec crossbar, a memory controller, PCI Gen2.0, 10 Gb Ethernet and cache coherency with 2.4 Tb/s bandwidth high-speed I/Os. The dual-issue, out-of-order execution core (S3) features a new 16-stage intege r pipeline, extensive branch predictions, dynamic threading and an enhanced cryptographic processing unit. The 406 mm die contains 855 million transis- tors and 2.6 million flip-flops in TSMC’s 40nm process utilizing 11 Cu metals and four transistor types. Enhanced physical design methodologies and extensive po wer management features enable 3.0 GHz operation in the same power envelope of its prede- cessor. Logically complex SRAMs deploy techniques to support out-of-order execution core while addressing area, timing and power challenges. The power supp ly calibration circuit improves yield by reducing 70% of conventional voltage guard-band for the speed and power constrained design.