A 24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication Meisam Honarvar Nazari , Student Member , IEEE

Abstract

This paper describes a dense, high-speed, and low-power CMOS optical receiver implemented in a 65-nm CMOS technology. High data rate is achieved using an RC double-sam- pling front-end and a novel dynamic offset-modulation technique. The low-voltage double-samplin g technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in transimpedance-ampli fier (TIA) receivers. In addi- tion, the demultiplexed output of the receiver helps save power in the following digital blocks. The receiver functionality was validated by electrical and optical measurements. The receiver achieves up to 24 Gb/s data rate with better than 160- Ac u r r e n t sensitivity in an experiment performed by a photodiode current emulator embedded on-chip. Opti cal measurements performed by a 1550-nm wire-bonded photodiode show better than 4.7-dBm optical sensitivity at 24 Gb/s. T he receiver offers peak power efficiency of 0.36 pJ/b at 20 Gb/s from a 1.2-V supply and occupies less than 0.0028 mm silicon area.