A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory Ki Chul Chun, Hui Zhao , Student Member , IEEE, Jonathan D. Harms

Abstract

This paper explores the scalability of in-plane and perpendicular MTJ based STT-MRAMs from 65 nm to 8 nm while taking into consideration re alistic variability effects. We focus on the read and write performances of a STT-MRAM based cache rather than the obvious advantages such as the denser bit-cell and zero static power. An accurate MTJ macromodel capturing key MTJ properties was adopted for ef ficient Monte Carlo simulations. For the simulation of access devices and pe- ripheral circuitries, ITRS projected transistor parameters were utilized and calibrated using the MASTAR tool that has been widely used in industry. 6T S RAM and STT-MRAM arrays were implemented with aggressive assist schemes to mimic industrial memory designs. A constant scaling scenario was used which to the first order gives the optimal balance between read and write margins of STT-MRAMs. The thermal stability factor ensuring a 10 year retention time was obtained by adjusting the free layer thickness as well as assuming improvement in the crystalline anisotropy. Our studi es based on the proposed scaling methodology show that in-plane STT-MRAM will outperform SRAM from 15 nm node, while its p erpendicular counterpart re- quires further innovations in MTJ material in order to overcome the poor write performance scaling from 22 nm node onwards .