A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ B

Abstract

This paper explores the scalability of in-plane and perpendicular MTJ based STT-MRAMs from 65 nm to 8 nm while taking into consideration re alistic variability effects. We focus on the read and write performances of a STT-MRAM based cache rather than the obvious advantages such as the denser bit-cell and zero static power. An accurate MTJ macromodel capturing key MTJ properties was adopted for ef ficient Monte Carlo simulations. For the simulation of access devices and pe- ripheral circuitries, I