JSSC 2013第2期Data Converters55nmDACPLL

Flying-Adder Fractional Divider Based Integer-N PLL 2nd Generation FAPLL as On-C

提出一种基于Flying-Adder分数分频器的第二代整数N锁相环，用于生成高纯度时钟信号。

55nm CMOS, 2.3GHz, 8.3mW, 0.16mm², 1.5MHz分辨率

Flying-Adder分数分频器整数N锁相环PDFR技术时钟生成

▸Flying-Adder合成器作为PLL环路内的分数分频器

▸采用PDFR技术提高频率分辨率

▸使用独特累加器提升电路速度

Abstract

Flying-Adder direct period synthesis is a technology that directly constructs output clock period from a know nb a s e time unit . In the past, it is mainly used for driving digital load. In this work, a new scheme is proposed to produce spectrally pure clock signal at certain frequencies which can be used to drive de- vices such as SoC on-chip ADC, DAC and etc. This scheme utilizes a Flying-Adder synthesizer as a fractional divider placed inside the PLL loop. Additionally, a PDFR technique is u