Flying-Adder Fractional Divider Based Integer-N PLL: 2nd Generation FAPLL as On-Chip Frequency Generator for SoC

Abstract

Flying-Adder direct period synthesis is a technology that directly constructs output clock period from a know nb a s e time unit . In the past, it is mainly used for driving digital load. In this work, a new scheme is proposed to produce spectrally pure clock signal at certain frequencies which can be used to drive de- vices such as SoC on-chip ADC, DAC and etc. This scheme utilizes a Flying-Adder synthesizer as a fractional divider placed inside the PLL loop. Additionally, a PDFR technique is use dt oh e l pi m - prove the frequency resolution. M oreover, a unique accumulator is used to boost circuit speed. A 55 nm implementation is fabri- cated and is used to validate the architectu re of this 2nd genera- tion Flying-Adder PLL. The resolution of this enhanced integer-N PLL is 1.5 MHz across the entire VCO operating range with a 12 MHz input and loop bandwidth of 1 MHz. The power consumed is 8.3 mW at 2.3 GHz and the area is 0.16 mm .T h es i g n ificance of this fractional divider is discussed at the end. A brief comparison between this clock generator and other s is given at the end as well.