Low-V oltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement Shu-Meng Y ang, Meng-Fan Chang, Chi-Chuang Chiang, Ming-Pin Chen, and Hiroyuki Y amauchi

Abstract

Density-prioritized memories such as NAND-ROM require a longer single-ended bitline (BL) sensing scheme to main- tain high cell array ef ficiency and therefore suffer from a reduced BL sensing margin at ultra-low supply voltages (VDD) for read-0. This is the result of 1) reduced BL discharge driving current due to limited cell size and driving voltage; and 2) a larger BL false drop noise for read-1. This study proposes a data-aware sensing reference (DASR) scheme, capable of maintaining sensing margins for both read-0 and read-1 under given timing constraints. The key mechanism involved in maintaining the sensing margin is the adaptive changing of the reference voltage , such that the sensing headroom or potential range for read-1 and read-0 overlap, as in differential BL sensing. Two 256 Kb DASR NAND-ROM macros, with and without code-inversion schemes, were fabricated using a 90 nm bulk CMOS logic process. The 256 Kb DASR NAND-ROM macros are functional down to 0.25 V. DASR also increases the access speed by 66.7% at 0.31 V VDD, compared with the conventional approach without the proposed DASR scheme.