← 返回 JSSC 论文列表JSSC 2013第3期Data Converters65nmPipeline ADCOp-Amp
A 10-Bit 300-MSs Pipelined ADC With Digital Calibration and Digital Bias Generat
采用65nm CMOS工艺的10位300MS/s流水线ADC，具有数字校准和数字偏置生成功能。
65nm CMOS, 1V, 300MS/s, 26.6mW, DNL 0.52/0.4 LSB, INL 0.99/1.65 LSB, SNDR 55.4 dB, SFDR 67.2 dB
流水线ADC数字校准数字偏置生成开关运放低功耗
▸创新点1：采用开关运放技术（电路创新），通过优化运放的开启时间设计，显著降低功耗，在300 MS/s采样率下仅消耗26.6 mW，同时保持高速性能。
▸创新点2：引入数字背景校准技术（系统创新），有效校正由运放低直流增益引起的A/D转换误差，使DNL和INL分别达到0.52/0.4 LSB和0.99/1.65 LSB的高精度水平。
▸创新点3：开发数字偏置电压生成电路（电路创新），自动调节运放偏置电压，确保运放的建立行为在工艺-电压-温度变化下保持稳定，提升整体可靠性。
▸创新点4：在65 nm CMOS工艺下实现高集成度（系统创新），芯片有效面积仅为0.36 mm²，同时兼顾10位分辨率和300 MS/s的高速采样性能。
Abstract
A 10-bit pipelined ADC was fabricated using a 65 nm
CMOS technology. To reduce power consumption, switching
opamps are used. Thes e switching opamps are designed to have a
short turn-on time. Digital backgr ound calibration is employed to
correct the A/D conversion error caused by the low dc gain of the
opamps. The biasing voltages in each opamp are automatically
generated using digital circuits. This bias scheme can maintain the
settling behavior of the opamp agai nst process-vol tage-tempera-