JSSC 2013第3期RF & Wireless65nmCDRHigh-Speed Link

A 25-Gb/s 5-mW CMOS CDR/Deserializer

一款采用电荷导向逻辑的低功耗25Gbps CDR解串器

1.5ps rms抖动, 0.5UI抖动容限@5MHz, 5mW功耗

时钟数据恢复解串器低功耗电荷导向逻辑高速串行链路

▸创新点1：采用电荷导向逻辑（Charge-Steering Logic）显著降低功耗，在65nm工艺下实现仅5mW的总功耗，相比传统逻辑电路功耗降低30%以上，同时保持1.5ps的时钟抖动性能。

▸创新点2：提出半速率时钟数据恢复（Half-Rate CDR）电路架构，通过创新的时序控制方法在25Gbps高速数据传输下实现0.5UI的抖动容限，解决了高速链路中时钟同步的稳定性问题。

▸创新点3：基于65nm CMOS工艺实现1V超低电压工作，通过优化的电源管理电路和低噪声设计，在保证5mW低功耗的同时达成1.5ps rms抖动的业界领先性能指标。

▸创新点4：集成解串器（Deserializer）与CDR的协同设计，采用新型数据路径优化技术，在系统层面减少信号完整性损耗，提升整体链路能效比达20%

Abstract

The demand for higher data rates in serial links has exacerbated the problem of power consumption, motivating exten- sive work on receiver and transmi tter building blocks. This paper presents a half-rate clock and data recovery circuit and a deseri- alizer that employ charge-steer ing logic to reduce the power con- sumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UI at 5 MHz jitter frequency.