JSSC 2013第3期Data Converters0.18μmDelta-Sigma ADCPLL

A 2832-GHz Fractional- Digital PLL With ADC-Assisted TDC and Inductively Coupled

一款2.8-3.2GHz分数数字PLL，采用0.18μm CMOS工艺，实现230fs抖动和240.4dB FOM。

0.18μm CMOS, 1.8V, 230fs rms jitter, 240.4dB FOM

分数数字PLLTDCADCdelta-sigma调制器电感耦合

▸ADC辅助TDC提升分辨率

▸电感耦合细调谐变容组改善调谐步长

▸三阶delta-sigma调制器量化噪声消除

Abstract

A 2.8–3.2-GHz fractional- digital PLL, imple- mented in 0.18- m CMOS, is presented. The PLL architecture has the form of a classic delta-sigma fractional- PLL. A PFD gen- erates up and down pulses from the reference and divided-down digitally controlled oscillator (DCO) clock. The time-to-digital converter (TDC) converts the wid th of up pulses to digital words. The quantization noise introduced by a third-order delta-sigma modulator through the multi-modulus divider is canceled at the TDC outpu