A 3 Megapixel 100 Fps 2.8 m Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers Shang-Fu Y eh, Chih-Cheng Hsieh, and Ka-Yi Y eh

Abstract

This paper presents a 3 megapixel 100 fps 2.8 m pixel pitch CMOS image sensor (CIS) layer with built-in self-test (BIST) for three-dimensional (3 D) integrated imagers. A modular CIS sub-array is proposed with new readout and control scheme. It needs only one micro-bump ( bump) per sub-array, instead of per-pixel or per-column, to release the design rule restriction of the 3D stacking process. The proposed readout structure with in-pixe l two-dimensional (2D) decoding fun ction achieves high spatial res- olution, without degrading the frame rate. A BIST circuit is also proposed to filter out unquali fied CIS layer before chip st acking, improving the yield performance of the final 3D integrated im- agers, without adding extra transistor in the pixel. A CIS chip with 16 8 sub-arrays and a pixel size of 2.8 2.8 m was fabricated in TSMC 0.18 m CIS process. The experimental results demon- strate the successful parallel o utput images of 3 megapixels with 16 8 modules at 100 fps. This shows that the imaging r esolution is expandable by the proposed modular sub-array design and is expected to achieve 100 fps at multi-mega imaging for high-speed HDTV camera applications.