A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-V ariation-Tolerant Current-Mode Read Schemes Meng-Fan Chang, Shyh-Shyuan Sheu, Ku-Feng Lin, Che-Wei Wu, Chia-Chen Kuo, Pi-Feng Chiu, Yih-Shan Y ang, Y u-Sheng Chen, Heng-Y uan Lee, Chen-Hsin Lien, Frederick T. Chen, Keng-Li Su, Tzu-Kun Ku, Ming-Jer Kao, and Ming-Jinn Tsai

Abstract

ReRAM is a promising next-gene ration nonvolatile memory (NVM) with fast write speed and low-power operation. However, ReRAM faces two major challenges in read operations: 1) low read yield due to wide resistanc e distribution and 2) the re- quirement of accurate bitline (BL) bias voltage control to prevent read disturbance. This study proposes two process-variation-tol- erant schemes for current-mode read operation of ReRAM: par- allel-series reference-cell (PSRC) and process-temperature-aware dynamic BL-bias (PTADB) schemes. These schemes are meant to improve the read speed and yield of ReRAM, while taking read dis- turbance into consideration. PSRC narrows the reference current distribution to achieve high read y ield against resistance variation. PTADB achieves small fluctuations in BL bias voltage to prevent read disturbance, while providing rapid BL precharge speeds. This study fabricated a 4-Mb ReRAM macro to con firm the effective- ness of the proposed sc hemes for both SLC and MLC operations. The fastest sub-8-ns (7.2 ns) rea d-write random access time among megabit scaled embedded NVM mac ros has been demonstrated.