← 返回 JSSC 论文列表JSSC 2013第3期Data Converters0.13μmTime-Interleaved ADCNeural Network Accelerator
A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design Seyed Danesh, Jed Hurwitz, Keith Findlater, David Renshaw, and
提出一种可重构的时间交织ADC架构，支持1GSps 7-bit至250MSps 9-bit的灵活配置。
0.13μm CMOS, 400fJ/step, 1GSps@7b/500MSps@8b/250MSps@9b
时间交织ADC可重构架构低噪声高线性度旋转电阻环
▸高度并行低带宽单斜率转换器阵列
▸基于旋转8字形电阻环的新型并行斜率斜坡发生器
▸实时可重构分辨率与采样率
Abstract
A recon figurable, highly time-interleaved ADC ar- chitecture that substantially decouples comparator requirements from input signal bandwidth and system sampling rate constraints is presented. A highly parallel array of low bandwidth, single slope converters achieves low noise and high linearity with very low input capacitance and signal-inde pendent current consumption. A 128-channel counter ADC, implemented in 0.13 mC M O S ,c a n be configured in real-time as a 1 GSps 7-bit, 500 MSps 8-bit, or 250 MSps 9-bit converter. Central to this approach is a novel parallel slope ramp-generator based on a rotating figure-of-8 resistor ring. The ADC achieves sub 400 fJ/step in all con figurations and a near flat SFDR over the entire input signal frequency range. The figure of merit scales favourably to nan ometer CMOS technologies.