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On-Chip Combined C-VI-V Characterization System in 45-nm CMOS Technology
45纳米CMOS工艺中实现片上C-V/I-V联合表征系统，用于研究器件变异性。
12-bit sub-10 nA电流分辨率, 10-bit sub-1 mV电压分辨率, 100 kHz采样速度, atto-Farad级电容分辨率
片上表征C-V/I-V测量CMOS技术器件变异性电荷基电容测量
▸四线开尔文测量技术实现12位亚10nA电流测量
▸新型抗泄漏和寄生的电荷基电容测量技术
▸首次实现电路代表性器件的C-V/I-V联合表征
Abstract
An on-chip system for comb ined capacitance-voltage
(C-V) and current-voltage (I-V) characterization of a large in-
tegrated transistor array implemented in a 45-nm bulk CMOS
process is presented. On-chip I-V characterization is implemented
using a four-point Kelvin measurement technique with 12-bit
sub-10 nA current measurement resolution, 10-bit sub-1 mV
voltage measurement resolution, and sampling speeds on the
order of 100 kHz. C-V characterization is performed using a novel
leakage- and par