AR e c o nfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB

Abstract

This paper presents a second-generation mostly-dig- ital background-calibrated ove rsampling ADC based on voltage- controlled ring oscillators (VCROs). Its performance is in line with the best modulator ADCs published to date, but it occupies much less circuit area, is recon figurable, and consists mainly of digital circuitry. Enhancements relative to the first-generation version include digitally back ground-calibrated open-loop conversion in the VCRO to increase ADC bandwidth and enable operation from a single low-voltage power supply, quadrature coupled ring oscillators to reduce quantization noise, digital over-range correction to improve dynamic range and enable graceful overload behavior, and various circuit-level improve- ments. The ADC occupies 0.075 mm i na6 5n mC M O Sp r o c e s s and operates from a single 0.9–1.2 V supply. Its sample-rate is tun- able from 1.3 to 2.4 GHz over which the SNDR spans 70–75 dB, the bandwidth spans 5–37.5 MHz, and the minimum SNDR+ 10log(bandwidth/power dissipation) figure of merit (FOM) is 160 dB.