A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-V oltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS Noriaki Maeda, Shigenobu Komatsu, Masao Mor imoto, Koji Tanaka, Y asumasa Tsukamoto

Abstract

We propose low-leakage current embedded SRAMs with high-performance for mob ile applications. The proposed SRAM has two standby modes depending on temperature; one is a low-voltage resume-standby mo de to reduce the standby current more effectively at room temperature, and the other is the conventional resume-standby to reduce effectively at high temperature. These schemes are implemented in a single SRAM macro with an all-digital current comparator (ADCC) that chooses either mode by monitoring automatically. ADCC has a time to digital converter (TDC) which is suitable for leakage measurement. Moreover, the pro posed monitoring sequence can compensate the error of the measurement caused by the variation of the MOSFETs. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 kb SRAM achieves 0.41 standby leakage which is half o f the conventional value. This SRAM also realizes a high-speed o peration with an access time of 420 ps.