A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply V oltage

Abstract

An all-digital dynamically adaptive clock distribution mitigates the impact of high -frequency supply voltage droops on microprocessor performance and energy ef ficiency. The design integrates a tunable-length delay prior to the global clock distribution to prolong the clock- data delay compensation in crit- ical paths during a droop. The tunable-length delay prevents critical-path timing-margin degr adation for multiple cycles after the droop occurs, thusa l l o w i n gas u fficient response time