A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply V oltage Droop Tolerance Keith A. Bowman , Member , IEEE

Abstract

An all-digital dynamically adaptive clock distribution mitigates the impact of high -frequency supply voltage droops on microprocessor performance and energy ef ficiency. The design integrates a tunable-length delay prior to the global clock distribution to prolong the clock- data delay compensation in crit- ical paths during a droop. The tunable-length delay prevents critical-path timing-margin degr adation for multiple cycles after the droop occurs, thusa l l o w i n gas u fficient response time for dynamic adaptation. An on-die dynamic variation monitor detects the onset of the droop to proactively gate the clock at the end of the tunable-length delay to eliminate the clock edges that would otherwise degrade critical-path timing margin. In comparison to a conventional clock distributi on, silicon measurements from a 22 nm test chip demonstrate sim ultaneous throughput gains and energy reductions of 14% and 3% at 1.0 V , 18% and 5% at 0.8 V , and 31% and 15% at 0.6 V , respectively, for a 10% droop.