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A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation Igor Arsovski, Travis Hebig, Daniel Dobson, and
32纳米工艺下采用早期预测-晚期校正技术的1GHz三态内容寻址存储器编译器，能效达0.58fJ/bit/search。
32nm HKMG SOI, 1Gsearch/sec, 2048x640bit, 0.76W, 0.58fJ/bit/search
三态内容寻址存储器早期预测能效优化深沟槽电容硅感知调谐
▸创新点1：早期预测-晚期校正(EPLC)传感技术通过两阶段搜索操作实现性能提升30%，方法创新在于提前激活主搜索并在预测错误时中断，显著降低延迟。
▸创新点2：嵌入式深沟槽(DT)电容技术通过减少53%的电源塌陷提升电源稳定性，电路创新在于仅增加5%面积开销的同时优化供电网络。
▸创新点3：硅感知调谐技术结合工艺特性优化TCAM编译器，系统创新实现1 Gsearch/sec吞吐量和0.58-fJ/bit/search能效，在32 nm工艺下面积仅1.56 mm²。
▸创新点4：两阶段搜索的动态功耗管理策略通过低概率的晚期校正机制，将错误预测对功耗的影响降至可忽略水平，属于功耗优化创新。
Abstract
A Ternary Content Addressable Mem ory (TCAM) uses a two-phase search operation where early prediction on its pre-search results premat urely activates the subsequent main-search operation, which is later int errupted only if the final pre-search results contradict the early prediction. This early main-search activation improve s performance by 30%, while the low-probability of a late-correct h as a negligible impact on power consumption. This Early-Predict Late-Correct (EPLC) sensing with silicon-aware tuning enables a high-performance TCAM compiler implemented in 32 nm High -K Metal Gate SOI process to achieve 1 Gsearch/sec throughput on a 2048x640 bit TCAM instance while consuming only 0.76 W, resulting in an energy efficiency of 0.58-fJ/bit/sear ch. Embedded Deep-Trench (DT) capacitance reduces power supply collapse by 53% while adding only 5% area overhead for a total TCAM area of 1.56 mm .