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A Harmonic-Rejecting CMOS LNA for
提出一种前端低噪声放大器中的谐波抑制技术，用于宽带射频接收机，以减轻谐波混频器的严格匹配要求。
65nm CMOS, 1.2V, 100 MHz to 10 GHz
谐波抑制低噪声放大器宽带射频CMOS频率响应
▸创新点1：谐波抑制技术 - 通过在低噪声放大器前端引入谐波抑制机制，显著降低了对谐波抑制混频器的严格匹配要求，提升了宽带射频接收机的抗干扰能力。
▸创新点2：频率响应整形技术 - 采用前馈和单向米勒电容倍增技术，实现了100 MHz至10 GHz信号带宽的频率响应整形，优化了信号处理性能。
▸创新点3：校准算法 - 提出了一种用于频率响应调谐的校准算法，确保了系统在不同工作条件下的稳定性和一致性，提高了系统的鲁棒性。
▸创新点4：电路实现与性能 - 采用65纳米数字CMOS技术制造的实验原型，在1.2V电源下功耗仅为8.64 mW，同时提供了至少20 dB的谐波抑制能力，展示了高效的电路设计和优异的性能指标。
Abstract
The local oscillator harmonics corrupt the desired signal in broadband RF receivers by downconverting interferers. This paper proposes the notion of harmonic rejection in the front-end low-noise ampli fier so as to relax the stringent matching required of harmonic-reject mixers. Described are frequency response shaping techniques by f eedforward and unilateral Miller capacitance multiplication for a signal bandwidth of 100 MHz to 10 GHz. A calibration algorithm is also proposed for the tuning of the frequency response. An experimental prototype fabricated in 65-nm digital CMOS technology provides at least 20 dB of rejection while consuming 8.64 mW with a 1.2-V supply.