A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Pow

Abstract

A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching reg ulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The par allel connection of the asyn- chronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion ef ficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchrono