An Integral Path Self-Calibration Scheme for a Dual-Loop PLL Mark Ferriss Jean-O

Abstract

An integral-path self-c alibration scheme is intro- duced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction schem e desensitizes the loop transfer function to the V CO’s small signal gain varia- tions. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of 126.5 dBc/Hz at