Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM Sami Rosenblatt, Daniel Fainstein, Alberto Cestero

Abstract

A random intrinsic chip ID generation method using r e t e n t i o nf a i l si si m p l e m e n t e di n3 2n mS O Ie m b e d d e dD R A M . A dynamic key algorithm employs a unique pair of 4 Kb binary strings for an ID record for secure authentication. These strings are generated by controlling a wordline low voltage to search for a number of fails matching the cor responding challenge numbers. The algorithm further includes field-tolerant authentication by de- tecting a number of common bits analytically guaranteed for suc- cessful recognition, while preventing ID spoo fing during the read operation. This results in 100% su ccessful unique ID generation and recognition in two temperatur e and three voltage conditions per chip for a total of 420 k ID pair comparisons in 266 chips. The analytical model predicts a 99.999% successful recognition rate for 10 parts. Finally, a method to enable a field-tolerant ID using mul- tiple domains will be discussed.