← 返回 JSSC 论文列表JSSC 2013第4期Memory65nm/40nmSRAM
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Usi
提出新型CSHBL和CCC技术，显著降低近阈值电压SRAM的能耗。
26.4 pJ/Access/Mbit (65nm), 13.8 pJ/Access/Mbit (40nm)
低电压SRAM能效优化电荷共享动态功耗近阈值电压
▸创新点1：CSHBL电荷共享技术（方法创新） - 通过分层次位线电荷共享方法，有效减少了SRAM在近阈值电压下的位线摆动，降低了因晶体管随机变异导致的额外功耗，实现了26.4 pJ/Access/Mbit的低能耗。
▸创新点2：CCC改进技术（电路创新） - 作为CSHBL的改进版本，CCC技术进一步优化了电荷共享机制，显著降低了非选中列的动态功耗，在40 nm工艺下实现了13.8 pJ/Access/Mbit的更低能耗。
▸创新点3：动态功耗优化（系统创新） - 通过创新的电荷共享和位线控制策略，系统性地减少了SRAM在低电压操作时的动态功耗，整体能耗表现优于以往研究。
▸创新点4：工艺适应性（可选） - 该技术在65 nm和40 nm工艺下均表现出优异的能耗特性，展示了其在先进工艺节点下的广泛适用性和可扩展性。
Abstract
Low voltage SRAM at a near-threshold voltage has
two major sources of power waste: excess bit line swing due to the
random variation of transistors and dynamic power consumption
of the bit line swing of non-selected columns. In order to overcome
these waste power consumption issues and achieve the highest
energy-efficient operation of low voltage SRAM, the new CSHBL
technique and CCC techniques, w hich is the improved version
of the CSHBL, have been propos ed. An SRAM fabricated using
65 nm techn