← 返回 JSSC 论文列表JSSC 2013第5期RF & Wireless65nmNeural Network Accelerator
A 047066 pJbit 488 Gbs IO Transceiver in 65 nm CMOS Y oung-Hoon Song Student Mem
一种低功耗转发时钟I/O收发器架构，采用高输出/输入复用和电压缩放技术。
4.8–8 Gb/s, 0.47–0.66 pJ/b, 0.5–0.8 V
低功耗I/O收发器电压模式驱动多相时钟注入锁定振荡器
▸创新点1：高输出/输入复用技术（系统创新）。该收发器采用4:1输出复用和1:8输入解复用技术，显著提高了数据传输效率，同时降低了功耗，实现了4.8-8 Gb/s的高速率传输。
▸创新点2：电压缩放与数据速率匹配（系统创新）。通过动态调整供电电压与数据速率匹配，优化了功耗效率，使得能量效率达到0.47-0.66 pJ/b，显著降低了整体能耗。
▸创新点3：低电压伪差分调节器（电路创新）。采用部分负电阻负载的低电压伪差分调节器，精确控制输出电压摆幅在100-200 mV之间，提高了低频增益和信号稳定性。
▸创新点4：8相注入锁定振荡器（电路创新）。接收端采用8相注入锁定振荡器，提供超过1UI的去偏斜范围，确保了多通道采样的精确同步，提高了接收器的时序容限。
Abstract
A low-power forwarded-cloc k I/O transceiver archi-
tecture is presented that employs a high degree of output/input
multiplexing, supply-voltage scaling with data rate, and
low-voltage circuit techniques to enable low-power operation.
The transmitter utilizes a 4:1 output multiplexing voltage-mode
driver along with 4-phase clocking that is ef ficiently generated
from a passive poly-phase filter. The output driver voltage
swing is accurately controlled from 100–200
using a
low-voltage pseudo-differ