A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM

Abstract

A quad-band GSM/GPRS/EDGE cellular system, implemented in 65-nm CMOS, is integrated in a m ultimedia SoC with BT and FM. A low-IF receiver with digital IRR tracking is selected for its smaller area and better noise figure. The receiver achieves a sensitivity of 110 dBm, an IIP3 of 9.5 dBm, and a calibrated image rejection ratio of 65 dBc, while consuming 61 mA. The polar transmitter architecture is chosen for its SA W-less TX capability, smaller area, and low curre nt consumption. It achieves an ORFS (output radio frequency spectrum) of 68 dB and 64 dB at 400 kHz in GMSK and EDGE mode, respectively, while consuming 61 mA. The loop gai n normalization, dc offset and AM/PM delay of the polar system are compensated to be better than 1% error, 1 mV , and 1.9 ns within 170 s, respectively. Several techniques are employe d to minimize interference cou- pling within the SoC; these include frequency planning, circuit implementation, transceiver archit ecture optimization, and digital clock selection. The measu red sensitivity and the output spectrum of the three wireless systems under full-feature phone operation are virtually unchanged.