A Linearized, Low-Phase-Noise VCO-Based 25-GHz PLL With

Abstract

This pap er describes a new approach to low-phase- noise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this lin- earization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase nois eo f 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the pape r introduces a new layout approach for switched capacitor arrays th at enables a wide tuning range of 23% . More than 1500 measurements of the PLL across PVT variations were taken, further va lidating the proposed design. Phase noise variation across 55 dies for four different frequencies is 0.6 dB. Also, phase noise variation across supply voltages of 0.7–1.5 V is 2 dB and across 60 temperature variation is 3 dB. At the 25 GHz center frequency, the VCO is 188 dBc/Hz. Additionally, a digitally assis ted autonomic bi asing technique is implemented in the PLL to pr ovide a phase noise and power optimized VCO bias across freque ncy and process. Measurement results indicate the ef ficacy of the autonomic biasing scheme.