JSSC 2013第5期Clocking & PLLs32nm SOI CMOSPLLVCO

A Linearized Low-Phase-Noise VCO-Based 25-GHz PLL With Autonomic Biasing Bodhisa

本文提出了一种基于线性化技术的低相位噪声25GHz VCO设计，并在32nm SOI CMOS工艺中实现。

32nm SOI CMOS, 0.7-1.5V, 25GHz, 130dBc/Hz@10MHz offset

低相位噪声VCO线性化技术自动偏置开关电容阵列

▸基于线性化技术的低相位噪声VCO设计

▸自动偏置技术优化相位噪声和功耗

▸新型开关电容阵列布局实现23%的调谐范围

Abstract

This pap er describes a new approach to low-phase- noise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this lin- earization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase nois eo f 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the pape r introduces a new layout approach for sw