← 返回 JSSC 论文列表JSSC 2013第6期Data Converters0.35-μm/0.5-μm CMOSDACOp-Amp
A 10-b Two-Stage DAC with an Area-Ef ficient Multiple-Output V oltage Selector an
提出一种用于LCD列驱动IC的10位两阶段DAC，采用面积高效的多输出电压选择器和线性增强的DAC嵌入式运放。
10位DAC，DNL/INL最差为0.44/0.58 LSB
DACLCD列驱动电压选择器线性增强CMOS
▸两阶段电压选择器设计（MSB和LSB解码器）
▸面积高效的多输出电压选择器架构
▸DAC嵌入式运放的线性增强技术
Abstract
This work proposes a 10-b two-stage DAC with an
area-efficient multiple-output voltage selector and a linearity-en-
hanced DAC-embedded op-amp for LCD column driver ICs.
The proposed voltage selector is divided into t wo stages, MSB
and LSB decoders; this design requires fewer switches compared
with tree-type voltage selectors, enabling a smaller die area. The
proposed 6-b two-voltage selector occu pies only 61% of the area
needed for a 6-b tree-type two-voltage selector. This study also
develops