A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms Meng-Fan Chang, Chih-Sheng Lin, Wei-Cheng Wu, Ming-Pin Chen, Y en-Huei Chen, Zhe-Hui Lin, Shyh-Shyuan Sheu, Tzu-Kun Ku, Cha-Hsin Lin, and Hiroyuki Y amauchi , Member , IEEE

Abstract

TSV-based 3D die-stacking technology enables the reuse of pre-desig ned, pre-tested logic dies stacked with multiple memory layers in various con figurations to form a universal-memory-capacity platform (UMCP). However, conven- tional 3D memori es suffer speed, power and yield overheads due to the large parasitic load of TSV and cross-layer PVT variations when implemented in large with wide IO, especially using via-la st TSVs. This work proposes a semi-master-slave (SMS) memory structure with sel f-timed differential-TSV signal transfer (STDT) scheme to improve the speed, power, and yield of 3D memory d evices, while providing high scalability in for 3D-UMCP. The SMS scheme achieves the following: 1) a constant-load logic-SRAM interface across various ;2 ) high tol erance for variations in cross-layer PVT, and 3) at-speed pre-bonding KGD sorting. The STDT scheme employs a TSV-load tracking scheme to achieve small TSV voltage swing for sup- pressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads, partic- ularly in UMCP designs with scalable and wide-IO. To verify the viability of the proposed structure and scheme, we developed a 2-layer 32 kb 3D-SRAM testchip with layer-scalable test-modes using a via-last TSV process with die-to-die bonding. This testchip con firmed the functionality and demonstrated supe- rior scalability in with small speed overheads.