A Resolution-Reconfigurable 5-to-10-Bit 0.4-to-1 V Power Scalable SAR ADC for

Abstract

A power-scalable SAR ADC for sensor applications is presented. The ADC features a recon figurable 5-to-10-bit DAC whose power scales exponentially with resolution. At low r esolu- tions where noise and linearity r equirements are reduced, supply voltage scaling is leveraged to further reduce the energy-per-con- version. The ADC operates up to 2 MS/s at 1 V and 5 kS/ sa t0 . 4 V , and its power scales linearly with sample rate down to leakage levels of 53 nW at 1 V and 4 nW at 0.4 V. Leakage power-gating during a SLEEP mode in between conversions redu ces total power by up to 14% at sample rates below 1 kS/s. Prototyped in a low- power 65 nm CMOS process, the ADC in 10-bit mode achieves an I N La n dD N Lo f0 . 5 7L S Ba n d0 . 5 8L S Br e s p e c t i vely at 0.6 V , and the Nyquist SNDR and SFDR are 55 dB and 69 dB respectively at 0.55 V and 20 kS/s. The ADC achieves an optimal FOM of 22.4 fJ/conversion-step at 0.55 V in 10-bi t mode. The combined tech- niques of DAC resolution and voltage scaling maximize ef ficiency at low resolutions, resulting in an FOM that increases by only 7x over the 5-bit scaling range, impro ving upon a 32x degradation that would otherwise arise from truncation of bits from an ADC of fixed resolution and voltage.