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JSSC 2013第6期Data Converters0.13 µm

A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step

提出一种采用噪声整形两步积分量化器的二阶ΔΣ ADC，实现高分辨率和一阶噪声整形。
峰值SNDR 70.7 dB，功耗8.1 mW，1.2 V电源，80 MHz采样频率
ΔΣ ADC噪声整形积分量化器CMOS反馈拓扑
▸噪声整形两步积分量化器：该方法创新性地结合了粗量化（flash ADC）和细量化（噪声整形积分量化器），实现了高分辨率和一阶噪声整形，提升了调制器的稳定性和整体性能。
▸结合模拟和数字信号的新型反馈拓扑：该电路创新通过独特的反馈结构，支持反馈-DAC的大量量化级别，优化了信号处理效率和系统适应性。
▸二阶噪声整形与一阶环路滤波器：该系统创新通过二阶噪声整形和一阶环路滤波器的结合，显著提高了ADC的信噪比和动态范围，实现了70.7 dB的峰值SNDR。
▸低功耗高性能设计：在0.13 µm CMOS工艺下，该设计以8.1 mW的功耗和1.2 V电源电压，实现了80 MHz采样频率下的高效能表现，展示了优异的能效比。
Abstract
In this paper, a new seco nd-order discrete-time ΔΣ ADC using a noise-shaped two-step integrating quantizer is presented. The first quantization step (coarse) is utilized with a flash ADC. The second quantization step ( fine) is implemented using a noise-shaped integrating quantizer. As a result, both high resolution and first-order noise shaping is achieved. High quan- tization resolution enhances the modulator stability whereas the extra order of noise-shaping imp roves the overall performance. The proposed ΔΣ ADC incorporating the noise-shaped two-step integrating quantizer manifests a second-order noise-shaping with a first-order loop filter. To accommodate the large number of quantization levels of the feedback-DAC, a new feedback topology is presented which uses both analog and digital signals. The pro- totype ADC is implemented in 0.13 µm CMOS and demonstrates peak SNDR of 70.7 dB while co nsuming 8.1 mW under a 1.2 V supply, with an OSR of 8 at 80 MHz sampling frequency.