Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

Abstract

A highly-digital clock multiplication arc hitecture that achieves excellent jitter and mitigates supply noise is pre- sented. The proposed architecture utilizes a calibration-free digital multiplying delay-locked loop (MDLL) to deco uple the tradeoff between time-to-digital converte r (TDC) resolution and oscillator phase noise in digital phase-locked loops (PLLs). Both reduction in jitter accumulation down to sub-picosecon d levels and improved supply noise rejection over conventional PLL architectures is demonstrated with low power consumption. A digital PLL that employs a 1-bit TDC and a low power regula tor that seeks to improve supply noise immunity wi thout increasing loop delay is presented and used to compare with the proposed MDLL. The prototype MDLL and DPLL chips are f abricated in a 0.13 m CMOS technology and operate fr om a nominal 1.1 V supply. The proposed MDLL achieves an integrated jitter of 400 fs rms at 1.5 GHz output frequency from a 3 75 MHz reference clock, while consuming 890 W. The worst-case supply noise sensitivity of the MDLL is 20 fs /mV which translates to a jitter degradation of 3.8 ps in the presence of 200 mV supply noise. The proposed clock multipliers occupy active die areas of 0.25 mm and 0.2 mm for the MDLL and DPLL, respectively.